Published by MVSST Power · October 2026
For most of the last decade the open question in solid-state transformer (SST) engineering was whether a suitable medium-voltage switch existed. That question has largely been answered: the 1.2 kV and 1.7 kV SiC platforms are mature, and 3.3 kV and above are in volume production for cascaded module counts. What remains is harder, because it is not a semiconductor problem.
The medium-frequency transformer (MFT) is the one component in an SST whose performance does not improve on a predictable cost curve. A power device improves because its material parameters and process node improve. An MFT improves only if winding process, insulation structure, curing stress and heat path are right at the same time — steps that do not scale like wafer fabrication. Five peer-reviewed papers published between August and September 2026 converge on the same conclusion: the MFT is now the binding constraint, and it can only be optimised as one coupled electrical–thermal–dielectric system.
The conventional approach to MFT insulation is to inherit the clearance and creepage rules of line-frequency dry-type transformers, then add margin. Korthauer and Biela argue this is both wasteful and unsafe, because insulation occupies a substantial fraction of total transformer volume — every unnecessary millimetre is paid for twice, in power density and in thermal resistance [2].
Their framework computes insulation distances instead of tabulating them. A two-step procedure produces universal design curves, so the required distance for a given design voltage can be read off inside a design optimisation loop. Validated on a foil-wound, air-insulated MFT using a physics-based model of discharge inception in air, the method produced a prototype with discharge well below 10 pC at a design voltage of 8.5 kV. Compared with conventional rules it permitted up to six times the design voltage while holding a safety margin above 100% relative to the maximum one-minute withstand voltage [2]. Insulation geometry is a design variable with a computable optimum, not an inherited constant.
A review by Adhikari and Ghassemi in IEEE Transactions on Dielectrics and Electrical Insulation synthesises the MV high-frequency insulation literature and reaches a conclusion that invalidates most single-factor derating practice: breakdown voltage, partial discharge inception voltage (PDIV) and electrical-treeing behaviour are not independently governed by frequency, temperature or waveform shape [1].
They emerge from coupled charge relaxation, dielectric-loss heating, local field enhancement, residual-charge memory and electro-thermal-mechanical damage. Beyond surveying, the paper proposes a normalised comparison framework — a voltage ratio Vn = V/V0 and fractional reduction RV = 1 − Vn — with review-level empirical scaling forms for breakdown/PDIV degradation and treeing rates under combined electrical, thermal and waveform stress [1].
Two outputs matter. First, a quantitative partial-discharge detection selection matrix for high-dv/dt square-wave and PWM excitation: not every PD method resolves the same defect under fast-edged waveforms. Second, mitigation is framed as multi-objective insulation coordination, and reliable design requires coordinated waveform definition, material qualification, diagnostic calibration, multiphysics modelling and system-level validation [1].
In a dual-active-bridge (DAB) stage the series inductance is the power-transfer element, not a parasitic: its value sets the power for a given phase shift. It used to come from an external inductor; the 2026 trend is to integrate it into the transformer — the leakage-inductance-integrated MFT (LI2MFT) [3].
Integration turns a magnetics job into multi-objective optimisation. The prototype reported by Noh, So, Park and Lee had to satisfy MV galvanic isolation, a target leakage inductance for DAB operation, efficiency, power density and thermal reliability at once — and because leakage inductance and losses depend nonlinearly on core shape, winding configuration and spatial layout, no closed-form solution exists [3].
Their answer was data-driven: 30 000 finite-element simulations trained machine-learning regressions for leakage inductance, losses and hotspot temperature rise, and NSGA-II produced a Pareto front over efficiency and volume. The fabricated 100 kW, 99% transformer-efficiency, 70 kV insulated prototype matched the model predictions [3]. The transferable point: when electrical and dielectric requirements are co-designed, a surrogate-model workflow is the only tractable way to explore the space.
Efficiency claims are only as good as the loss model behind them; under non-sinusoidal DAB excitation the standard models are systematically optimistic. Liu et al. quantify the error on a 300 V, 6 kVA, 50 kHz ferrite foil-wound transformer; the test article is below medium voltage, but the modelling lesson transfers [5].
On the core side, applying the improved generalised Steinmetz equation (iGSE) to the whole core as if flux were uniform gave 1.63 W. Splitting the shell-type core into legs, side pillars and yokes, deriving a region-specific flux-density waveform from the single-phase-shift model, and applying iGSE per region gave 1.11 W against 1.14 W from COMSOL. The uniform-flux assumption is the dominant error term [5].
On the winding side, FFT decomposition with frequency-dependent skin depth through the seventh harmonic, fed into a Dowell model, predicted 34.59 W against 41.20 W from finite elements. The gap is the one-dimensional field assumption: edge current crowding, winding-end leakage flux and local fringing are not represented. Against open- and short-circuit measurements the combined method held core loss to within 10–15% and winding loss to within 8–10% [5].
In a dry-type MFT the thick epoxy that provides dielectric withstand is also the material between winding hotspot and cold plate, and its thermal conductivity is low by construction. Thermal design is therefore not an add-on to insulation design; it competes with it.
Liu et al. embed high-thermal-conductivity heat pipes inside the transformer body, so internal heat conducts out to heat sinks and fans rather than through the insulation [4]. Their 20 kHz, 750 V/680 V, 70 kW prototype for a 10 kV SST reached 99.53% transformer efficiency, 10.41 kW/L and a 106 °C hotspot, with the heat-pipe scheme lowering hotspot temperature relative to conventional cooling [4].
| Design question | 2026 finding | Where it bites |
|---|---|---|
| How much insulation distance? | Computable from universal design curves; up to 6× design voltage vs conventional rules, <10 pC at 8.5 kV [2] | Over-margined geometry costs both power density and thermal resistance |
| How does insulation fail? | Coupled electrical–thermal–waveform mechanisms; single-factor derating does not predict it [1] | Type tests and PD diagnostics must match the real switching waveform |
| Where does DAB inductance come from? | Integrated into the transformer; 100 kW / 99% / 70 kV prototype designed by ML + NSGA-II [3] | Leakage tolerance becomes power-sharing tolerance between parallel units |
| How accurate is the loss model? | Region-partitioned core loss, harmonic-resolved winding loss; within 10–15% / 8–10% of measurement [5] | Uniform-flux iGSE over-predicts core loss by roughly a third in the reported case |
| How is heat removed? | Heat pipes embedded in the body; 70 kW / 10 kV unit at 99.53%, 10.41 kW/L, 106 °C [4] | Insulation and cooling compete for the same volume |
Related: Medium-Voltage SST Topologies, Control and the Engineering Gap · SiC Technology in Medium Voltage Applications · MV SST vs Traditional Transformer
Disclaimer: This article is a technical summary compiled from the publicly available peer-reviewed sources listed above for industry information purposes only. Reported figures are component-level results under the conditions stated in each paper and are not system-level guarantees. Design decisions on a specific project require project-specific engineering analysis.
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